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| Low Power, Selectable Gain Differential ADC Driver, G = 1, 2, 3 ADA4950-1/ADA4950-2 FEATURES High performance at low power High speed -3 dB bandwidth of 750 MHz, G = 1 0.1 dB flatness to 210 MHz, VOUT, dm = 2 V p-p, RL, dm = 200 Slew rate: 2900 V/s, 25% to 75% Fast 0.1% settling time of 9 ns Low power: 9.5 mA per amplifier Low harmonic distortion 108 dB SFDR @ 10 MHz 98 dB SFDR @ 20 MHz Low output voltage noise: 9.2 nV/Hz, G = 1, RTO 0.2 mV typical input offset voltage Selectable differential gains of 1, 2, and 3 Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Input common-mode range shifted down by 1 VBE Wide supply range: +3 V to 5 V Available in 16-lead and 24-lead LFCSP packages FUNCTIONAL BLOCK DIAGRAMS 16 -VS 15 -VS 13 -VS 12 PD 11 -OUT 10 +OUT 9 VOCM +INB 1 +INA 2 -INA 3 +INB 4 ADA4950-1 14 -VS +VS 7 +VS 8 +VS 5 Figure 1. ADA4950-1 +INA1 +INB1 -VS1 -VS1 PD1 -OUT1 -INA1 -INB1 +VS1 +VS1 +INB2 +INA2 1 2 3 4 5 6 24 23 22 21 20 19 +VS 6 ADA4950-2 18 17 16 15 14 13 +OUT1 VOCM1 -VS2 -VS2 PD2 -OUT2 HARMONIC DISTORTION (dBc) ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers Figure 2. ADA4950-2 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 1 10 FREQUENCY (MHz) 100 07957-025 VOUT, dm = 2V p-p GENERAL DESCRIPTION The ADA4950-1/ADA4950-2 are gain-selectable versions of the ADA4932-1/ADA4932-2 with on-chip feedback and gain resistors. They are ideal choices for driving high performance ADCs as singleended-to-differential or differential-to-differential amplifiers. The output common-mode voltage is user adjustable by means of an internal common-mode feedback loop, allowing the ADA4950-1/ ADA4950-2 output to match the input of the ADC. The internal feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. Differential gain configurations of 1, 2, and 3 are easily realized with internal feedback networks that are connected externally to set the closed-loop gain of the amplifier. The ADA4950-1/ADA4950-2 are fabricated using the Analog Devices, Inc., proprietary silicon-germanium (SiGe) complementary bipolar process, enabling them to achieve low levels of distortion and noise at low power consumption. The low offset and excellent dynamic performance of the ADA4950-x make it well suited for a wide variety of data acquisition and signal processing applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. HD2, 5V HD3, 5V HD2, 2.5V HD3, 2.5V -140 0.1 Figure 3. Harmonic Distortion vs. Frequency at Various Supplies The ADA4950-x is available in a Pb-free, 3 mm x 3 mm, 16-lead LFCSP (ADA4950-1, single) or a Pb-free, 4 mm x 4 mm, 24-lead LFCSP (ADA4950-2, dual). The pinout has been optimized to facilitate PCB layout and minimize distortion. The ADA4950-1/ ADA4950-2 are specified to operate over the -40C to +105C temperature range; both operate on supplies from +3 V to 5 V. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved. -INA2 -INB2 +VS2 +VS2 VOCM2 +OUT2 07957-002 APPLICATIONS 7 8 9 10 11 12 07957-001 ADA4950-1/ADA4950-2 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Operation ............................................................................. 3 5 V Operation ............................................................................... 5 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Maximum Power Dissipation ..................................................... 7 ESD Caution .................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Test Circuits ..................................................................................... 16 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18 Applications Information .............................................................. 19 Analyzing an Application Circuit ............................................ 19 Selecting the Closed-Loop Gain............................................... 19 Estimating the Output Noise Voltage ...................................... 19 Calculating the Input Impedance for an Application Circuit ....................................................................................................... 20 Input Common-Mode Voltage Range ..................................... 22 Input and Output Capacitive AC Coupling ............................ 22 Input Signal Swing Considerations .......................................... 22 Setting the Output Common-Mode Voltage .......................... 22 Layout, Grounding, and Bypassing .............................................. 23 High Performance ADC Driving ................................................. 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 REVISION HISTORY 5/09--Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADA4950-1/ADA4950-2 SPECIFICATIONS 5 V OPERATION TA = 25C, +VS = 5 V, -VS = -5 V, VOCM = 0 V, G = 1, RT = 53.6 (when used), RL, dm = 1 k, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 52 for signal definitions. Differential Inputs to VOUT, dm Performance Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Small-Signal Bandwidth -3 dB Large-Signal Bandwidth Bandwidth for 0.1 dB Flatness ADA4950-1 ADA4950-2 Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Test Conditions/Comments VOUT, dm = 0.1 V p-p VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p, RL = 200 Min Typ 750 350 210 230 2900 9 20 Max Unit MHz MHz MHz MHz V/s ns ns Third Harmonic IMD3 Voltage Noise (Referred to Output) Crosstalk (ADA4950-2) INPUT CHARACTERISTICS Offset Voltage (Referred to Input) Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Gain Error VOUT, dm = 2 V p-p, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 5 V ramp, G = 2 See Figure 51 for distortion test circuit VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p f = 1 MHz Gain = 1 Gain = 2 Gain = 3 f = 10 MHz; Channel 2 active, Channel 1 output V+DIN = V-DIN = VOCM = 0 V TMIN to TMAX variation Single-ended at package pin Directly at internal amplifier inputs, not external input terminals DC, VOUT, dm/VIN, cm, VIN, cm = 1 V -2.5 -108 -107 -98 -80 -126 -105 -99 -84 -94 9.2 12.5 16.6 -87 dBc dBc dBc dBc dBc dBc dBc dBc dBc nV/Hz nV/Hz nV/Hz dB 64 Maximum VOUT, single-ended output, RL = 1 k 200 kHz, RL, dm = 10 , SFDR = 69 dB VOUT, cm/VOUT, dm, VOUT, dm = 2 V p-p, 1 MHz; see Figure 50 for output balance test circuit Gain = 1 Gain = 2 Gain = 3 -VS + 1.4 to +VS - 1.4 0.2 -3.7 0.5 -VS + 0.2 to +VS - 1.8 -64 66 -VS + 1.2 to +VS - 1.2 114 -62 0.5 1.0 0.8 +2.5 mV V/C pF V dB dB V mA peak dB -49 1.2 1.9 1.7 % % % Rev. 0 | Page 3 of 28 ADA4950-1/ADA4950-2 VOCM to VOUT, cm Performance Table 2. Parameter VOCM DYNAMIC PERFORMANCE -3 dB Small-Signal Bandwidth -3 dB Large-Signal Bandwidth Slew Rate Input Voltage Noise (Referred to Input) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Test Conditions/Comments VOUT, cm = 100 mV p-p VOUT, cm = 2 V p-p VIN = 1.5 V to 3.5 V, 25% to 75% f = 1 MHz Min Typ 250 105 430 9.8 -VS + 1.2 to +VS - 1.2 26 +0.8 -60 1.0 Max Unit MHz MHz V/s nV/Hz V 32 +6 -49 1.01 k mV dB V/V V+DIN = V-DIN = 0 V VOUT, dm/VOCM, VOCM = 1 V VOUT, cm/VOCM, VOCM = 1 V 22 -6 0.98 General Performance Table 3. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Test Conditions/Comments Min 3.0 8.8 TMIN to TMAX variation Powered down VOUT, dm/VS, VS = 1 V p-p Powered down Enabled Typ Max 11 10.1 1.0 -84 Unit V mA A/C mA dB V V ns ns +1.0 -140 +105 A A C Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled OPERATING TEMPERATURE RANGE 9.5 31 0.7 -96 (+VS - 2.5) (+VS - 1.8) 600 28 PD = 5 V PD = 0 V -1.0 -250 -40 +0.2 -180 Rev. 0 | Page 4 of 28 ADA4950-1/ADA4950-2 5 V OPERATION TA = 25C, +VS = 5 V, -VS = 0 V, VOCM = 2.5 V, G = 1, RT = 53.6 (when used), RL, dm = 1 k, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 52 for signal definitions. Differential Inputs to VOUT, dm Performance Table 4. Parameter DYNAMIC PERFORMANCE -3 dB Small-Signal Bandwidth -3 dB Large-Signal Bandwidth Bandwidth for 0.1 dB Flatness ADA4950-1 ADA4950-2 Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Test Conditions/Comments VOUT, dm = 0.1 V p-p VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p, RL = 200 Min Typ 770 320 220 160 2200 10 19 Max Unit MHz MHz MHz MHz V/s ns ns Third Harmonic IMD3 Voltage Noise (Referred to Input) Crosstalk (ADA4950-2) INPUT CHARACTERISTICS Offset Voltage (Referred to Input) Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Gain OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Gain Error VOUT, dm = 2 V p-p, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 2.5 V ramp, G = 2 See Figure 51 for distortion test circuit VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz VOUT, dm = 2 V p-p 1 MHz 10 MHz 20 MHz 50 MHz f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p f = 1 MHz Gain = 1 Gain = 2 Gain = 3 f = 10 MHz; Channel 2 active, Channel 1 output V+DIN = V-DIN = VOCM = 2.5 V TMIN to TMAX variation Single-ended at package pin Directly at internal amplifier inputs, not external input terminals DC, VOUT, dm/VIN, cm, VIN, cm = 1 V -4 -108 -107 -98 -82 -124 -114 -99 -83 -94 9.2 12.5 16.6 -87 dBc dBc dBc dBc dBc dBc dBc dBc dBc nV/Hz nV/Hz nV/Hz dB 64 Maximum VOUT, single-ended output, RL = 1 k 200 kHz, RL, dm = 10 , SFDR = 67 dB VOUT, cm/VOUT, dm, VOUT, dm = 1 V p-p, 1 MHz; see Figure 50 for output balance test circuit Gain = 1 Gain = 2 Gain = 3 -VS + 1.2 to +VS - 1.2 0.4 -3.7 0.5 -VS + 0.2 to +VS - 1.8 -64 66 -VS + 1.1 to +VS - 1.1 70 -62 0.5 1.0 0.8 +4 mV V/C pF V dB dB V mA peak dB -49 1.2 1.9 1.7 % % % Rev. 0 | Page 5 of 28 ADA4950-1/ADA4950-2 VOCM to VOUT, cm Performance Table 5. Parameter VOCM DYNAMIC PERFORMANCE -3 dB Small-Signal Bandwidth -3 dB Large-Signal Bandwidth Slew Rate Input Voltage Noise (Referred to Input) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Test Conditions/Comments VOUT, cm = 100 mV p-p VOUT, cm = 2 V p-p VIN = 1.5 V to 3.5 V, 25% to 75% f = 1 MHz Min Typ 240 90 380 9.8 -VS + 1.2 to +VS - 1.2 26 +1.0 -60 1.0 Max Unit MHz MHz V/s nV/Hz V 32 +6.5 -49 1.01 k mV dB V/V V+DIN = V-DIN = 2.5 V VOUT, dm/VOCM, VOCM = 1 V VOUT, cm/VOCM, VOCM = 1 V 22 -6.5 0.98 General Performance Table 6. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Test Conditions/Comments Min 3.0 8.4 TMIN to TMAX variation Powered down VOUT, dm/VS, VS = 1 V p-p Powered down Enabled Typ Max 11 9.6 0.9 -84 Unit V mA A/C mA dB V V ns ns +1.0 -40 +105 A A C Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled OPERATING TEMPERATURE RANGE 8.9 31 0.6 -96 (+VS - 2.5) (+VS - 1.8) 600 29 PD = 5 V PD = 0 V -1.0 -100 -40 +0.2 -65 Rev. 0 | Page 6 of 28 ADA4950-1/ADA4950-2 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Power Dissipation Input Current, +INx, -INx, PD Storage Temperature Range Operating Temperature Range ADA4950-1 ADA4950-2 Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 11 V See Figure 4 5 mA -65C to +125C -40C to +105C -40C to +105C 300C 150C The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power dissipated due to the load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 16-lead LFCSP (91C/W) and the dual 24-lead LFCSP (65C/W) on a JEDEC standard 4-layer board with the exposed pad soldered to a PCB pad that is connected to a solid plane. 3.5 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p printed circuit board, as described in EIA/JESD51-7. Table 8. Thermal Resistance Package Type ADA4950-1, 16-Lead LFCSP (Exposed Pad) ADA4950-2, 24-Lead LFCSP (Exposed Pad) JA 91 65 JC 28 16 Unit C/W C/W MAXIMUM POWER DISSIPATION (W) 3.0 2.5 2.0 ADA4950-2 1.5 ADA4950-1 1.0 MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4950-x package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4950-x. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices, potentially causing failure. 0 -40 -20 60 0 20 40 AMBIENT TEMPERATURE (C) 80 100 Figure 4. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION Rev. 0 | Page 7 of 28 07957-004 0.5 ADA4950-1/ADA4950-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 16 -VS 15 -VS 14 -VS 13 -VS +INB 1 +INA 2 -INA 3 -INB 4 PIN 1 INDICATOR 12 PD 11 -OUT 10 +OUT 9 VOCM ADA4950-1 TOP VIEW (Not to Scale) -INA1 -INB1 +VS1 +VS1 +INB2 +INA2 1 2 3 4 5 6 24 23 22 21 20 19 PIN 1 INDICATOR +INA1 +INB1 -VS1 -VS1 PD1 -OUT1 18 17 16 15 14 13 ADA4950-2 TOP VIEW (Not to Scale) +OUT1 VOCM1 -VS2 -VS2 PD2 -OUT2 +VS 5 +VS 6 +VS 8 +VS 7 Figure 5. ADA4950-1 Pin Configuration Figure 6. ADA4950-2 Pin Configuration Table 9. ADA4950-1 Pin Function Descriptions Pin No. 1 2 3 4 5 to 8 9 10 11 12 13 to 16 17 (EPAD) Mnemonic +INB +INA -INA -INB +VS VOCM +OUT -OUT PD -VS Exposed Paddle (EPAD) Description Positive Input B, 250 Input. Use alone for G = 2 or tie to +INA for G = 3. Positive Input A, 500 Input. Use alone for G = 1 or tie to +INB for G = 3. Negative Input A, 500 Input. Use alone for G = 1 or tie to -INB for G = 3. Negative Input B, 250 Input. Use alone for G = 2 or tie to -INA for G = 3. Positive Supply Voltage. Output Common-Mode Voltage. Positive Output. Negative Output. Power-Down Pin. Negative Supply Voltage. Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Table 10. ADA4950-2 Pin Function Descriptions Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 25 (EPAD) Mnemonic -INA1 -INB1 +VS1 +INB2 +INA2 -INA2 -INB2 +VS2 VOCM2 +OUT2 -OUT2 PD2 -VS2 VOCM1 +OUT1 -OUT1 PD1 -VS1 +INB1 +INA1 Exposed Paddle (EPAD) Description Negative Input A, Amplifier 1, 500 Input. Use alone for G = 1 or tie to -INB1 for G = 3. Negative Input B, Amplifier 1, 250 Input. Use alone for G = 2 or tie to -INA1 for G = 3. Positive Supply Voltage, Amplifier 1. Positive Input B, Amplifier 2, 250 Input. Use alone for G = 2 or tie to +INA2 for G = 3. Positive Input A, Amplifier 2, 500 Input. Use alone for G = 1 or tie to +INB2 for G = 3. Negative Input A, Amplifier 2, 500 Input. Use alone for G = 1 or tie to -INB2 for G = 3. Negative Input B, Amplifier 2, 250 Input. Use alone for G = 2 or tie to -INA2 for G = 3. Positive Supply Voltage, Amplifier 2. Output Common-Mode Voltage, Amplifier 2. Positive Output, Amplifier 2. Negative Output, Amplifier 2. Power-Down Pin, Amplifier 2. Negative Supply Voltage, Amplifier 2. Output Common-Mode Voltage, Amplifier 1. Positive Output, Amplifier 1. Negative Output, Amplifier 1. Power-Down Pin, Amplifier 1. Negative Supply Voltage, Amplifier 1. Positive Input B, Amplifier 1, 250 Input. Use alone for G = 2 or tie to +INA1 for G = 3. Positive Input A, Amplifier 1, 500 Input. Use alone for G = 1 or tie to +INB1 for G = 3. Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Rev. 0 | Page 8 of 28 07957-006 NOTES 1. SOLDER THE EXPOSED PADDLE ON THE BACK OF THE PACKAGE TO A GROUND PLANE OR TO A POWER PLANE. 07957-005 NOTES 1. SOLDER THE EXPOSED PADDLE ON THE BACK OF THE PACKAGE TO A GROUND PLANE OR TO A POWER PLANE. -INA2 -INB2 +VS2 +VS2 VOCM2 +OUT2 7 8 9 10 11 12 ADA4950-1/ADA4950-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, +VS = 5 V, -VS = -5 V, VOCM = 0 V, G = 1, RT = 53.6 (when used), RL, dm = 1 k, unless otherwise noted. Refer to Figure 49 for test setup. Refer to Figure 52 for signal definitions. 2 2 NORMALIZED CLOSED-LOOP GAIN (dB) VOUT, dm = 100mV p-p NORMALIZED CLOSED-LOOP GAIN (dB) 1 0 -1 -2 -3 -4 -5 -6 1 0 -1 -2 -3 -4 -5 -6 -7 -8 1 VOUT, dm = 2V p-p G = 1, RT = 53.6 G = 2, RT = 57.6 G = 3, RT = 61.9 G = 1, RT = 53.6 G = 2, RT = 57.6 G = 3, RT = 61.9 -7 -8 1 10 100 FREQUENCY (MHz) 1000 10 100 FREQUENCY (MHz) 1000 Figure 7. Small-Signal Frequency Response for Various Gains 2 1 0 CLOSED-LOOP GAIN (dB) Figure 10. Large-Signal Frequency Response for Various Gains 2 VOUT, dm = 100mV p-p 1 0 VOUT, dm = 2V p-p -1 -2 -3 -4 -5 -6 VS = 5V VS = 2.5V CLOSED-LOOP GAIN (dB) -1 -2 -3 -4 -5 -6 VS = 5V VS = 2.5V 07957-008 -7 -8 1 10 100 FREQUENCY (MHz) 1000 -7 -8 1 10 100 FREQUENCY (MHz) 1000 Figure 8. Small-Signal Frequency Response for Various Supplies 2 1 0 CLOSED-LOOP GAIN (dB) Figure 11. Large-Signal Frequency Response for Various Supplies 2 VOUT, dm = 100mV p-p 1 0 CLOSED-LOOP GAIN (dB) VOUT, dm = 2V p-p -1 -2 -3 -4 -5 -6 TA = -40C TA = +25C TA = +105C -1 -2 -3 -4 -5 -6 TA = -40C TA = +25C TA = +105C 07957-009 -7 -8 1 10 100 FREQUENCY (MHz) 1000 -7 -8 1 10 100 FREQUENCY (MHz) 1000 Figure 9. Small-Signal Frequency Response for Various Temperatures Figure 12. Large-Signal Frequency Response for Various Temperatures Rev. 0 | Page 9 of 28 07957-012 07957-011 07957-010 07957-007 ADA4950-1/ADA4950-2 2 1 0 CLOSED-LOOP GAIN (dB) 2 VOUT, dm = 100mV p-p 1 0 CLOSED-LOOP GAIN (dB) VOUT, dm = 2V p-p -1 -2 -3 -4 -5 -6 RL = 1k RL = 200 -1 -2 -3 -4 -5 -6 RL = 1k RL = 200 07957-013 -7 -8 1 10 100 FREQUENCY (MHz) 1000 -7 -8 1 10 100 FREQUENCY (MHz) 1000 Figure 13. Small-Signal Frequency Response at Various Loads 2 1 0 CLOSED-LOOP GAIN (dB) Figure 16. Large-Signal Frequency Response at Various Loads 2 VOUT, dm = 100mV p-p 1 0 CLOSED-LOOP GAIN (dB) VOUT, dm = 2V p-p -1 -2 -3 -4 -5 -6 VOCM = -2.5VDC VOCM = 0V VOCM = +2.5VDC -1 -2 -3 -4 -5 -6 VOCM = -2.5VDC VOCM = 0V VOCM = +2.5VDC 07957-014 -7 -8 1 10 100 FREQUENCY (MHz) 1000 -7 -8 1 10 100 FREQUENCY (MHz) 1000 Figure 14. Small-Signal Frequency Response for Various VOCM Levels 4 VOUT, dm = 100mV p-p 2 CLOSED-LOOP GAIN (dB) Figure 17. Large-Signal Frequency Response for Various VOCM Levels 4 2 CLOSED-LOOP GAIN (dB) VOUT, dm = 2V p-p 0 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF 0 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF -2 -2 -4 -4 -6 07957-015 -6 07957-018 -8 1 10 100 FREQUENCY (MHz) 1000 -8 1 10 100 FREQUENCY (MHz) 1000 Figure 15. Small-Signal Frequency Response at Various Capacitive Loads Figure 18. Large-Signal Frequency Response at Various Capacitive Loads Rev. 0 | Page 10 of 28 07957-017 07957-016 ADA4950-1/ADA4950-2 0.5 0.4 0.3 VOUT, dm = 100mV p-p 0.5 0.4 0.3 CLOSED-LOOP GAIN (dB) VOUT, dm = 2V p-p CLOSED-LOOP GAIN (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1 10 100 FREQUENCY (MHz) ADA4950-1, ADA4950-1, ADA4950-2, ADA4950-2, ADA4950-2, ADA4950-2, RL = 1k R L = 200 AMP 1, RL = 1k AMP 1, RL = 200 AMP 2, RL = 1k AMP 2, RL = 200 0.2 0.1 0 -0.1 -0.2 -0.3 ADA4950-1, ADA4950-1, ADA4950-2, ADA4950-2, ADA4950-2, ADA4950-2, RL = 1k R L = 200 AMP 1, RL = 1k AMP 1, RL = 200 AMP 2, RL = 1k AMP 2, RL = 200 -0.4 -0.5 1 1000 10 100 FREQUENCY (MHz) 1000 Figure 19. 0.1 dB Flatness, Small-Signal Frequency Response for Various Loads 2 1 0 -1 VOCM = -2.5VDC VOCM = 0V VOCM = +2.5VDC VOCM (AC) = 100mV p-p Figure 22. 0.1 dB Flatness, Large-Signal Frequency Response for Various Loads 2 1 0 -1 VOCM GAIN (dB) VOCM (AC) = 2V p-p VOCM GAIN (dB) -2 -3 -4 -5 -6 -7 -8 1 -2 -3 -4 -5 -6 -7 -8 1 VOCM = -2.5VDC VOCM = 0V VOCM = +2.5VDC 10 100 FREQUENCY (MHz) 1000 10 100 FREQUENCY (MHz) 1000 Figure 20. VOCM Small-Signal Frequency Response at Various DC Levels -40 -50 HARMONIC DISTORTION (dBc) Figure 23. VOCM Large-Signal Frequency Response at Various DC Levels -40 -50 HARMONIC DISTORTION (dBc) VOUT, dm = 2V p-p VOUT, dm = 2V p-p HD2, HD3, HD2, HD3, HD2, HD3, G G G G G G =1 =1 =2 =2 =3 =3 -60 -70 -80 -90 -100 -110 -120 -130 HD2, RL, dm = 1k HD3, RL, dm = 1k HD2, RL, dm = 200 HD3, RL, dm = 200 -60 -70 -80 -90 -100 -110 -120 -130 07957-021 1 10 FREQUENCY (MHz) 100 1 10 FREQUENCY (MHz) 100 Figure 21. Harmonic Distortion vs. Frequency at Various Loads Figure 24. Harmonic Distortion vs. Frequency at Various Gains Rev. 0 | Page 11 of 28 07957-024 -140 0.1 -140 0.1 07957-023 07957-020 07957-022 07957-019 ADA4950-1/ADA4950-2 -40 -50 HARMONIC DISTORTION (dBc) VOUT, dm = 2V p-p -40 -50 VOCM = 0V HD2, HD3, HD2, HD3, 5V 5V 2.5V 2.5V -70 -80 -90 -100 -110 -120 -130 HD2, 5V HD3, 5V HD2, 2.5V HD3, 2.5V HARMONIC DISTORTION (dBc) 07957-025 -60 -60 -70 -80 -90 -100 -110 -120 -130 1 10 FREQUENCY (MHz) 100 0 1 2 3 4 5 8 9 6 7 VOUT, dm (V p-p) 10 11 12 13 14 Figure 25. Harmonic Distortion vs. Frequency at Various Supplies -40 Figure 28. Harmonic Distortion vs. VOUT, dm, f = 10 MHz -30 -40 HARMONIC DISTORTION (dBc) VOUT, dm = 2V p-p -50 VOUT, dm = 2V p-p HD2 AT HD3 AT HD2 AT HD3 AT 10MHz 10MHz 30MHz 30MHz HARMONIC DISTORTION (dBc) -50 -60 -70 -80 -90 -100 -110 -120 -3 -2 -1 0 VOCM (V) 1 2 3 4 07957-026 HD2 AT HD3 AT HD2 AT HD3 AT 10MHz 10MHz 30MHz 30MHz -60 -70 -80 -90 -100 -110 -120 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VOCM (V) Figure 26. Harmonic Distortion vs. VOCM at Various Frequencies, 5 V Supplies Figure 29. Harmonic Distortion vs. VOCM at Various Frequencies, 5 V Supply -50 -40 SPURIOUS-FREE DYNAMIC RANGE (dBc) -50 HARMONIC DISTORTION (dBc) VOUT, dm = 2V p-p -60 -70 -80 -90 -100 -110 -120 -130 07957-030 -60 -70 -80 -90 -100 -110 -120 -130 HD2, VOUT, dm = 2V p-p HD3, VOUT, dm = 2V p-p HD2, VOUT, dm = 4V p-p HD3, VOUT, dm = 4V p-p RL, dm = 200 RL, dm = 1k 1 10 FREQUENCY (MHz) 100 07957-027 -140 0.1 -140 0.1 1 10 FREQUENCY (MHz) 100 Figure 27. Harmonic Distortion vs. Frequency at Various VOUT, dm Figure 30. Spurious-Free Dynamic Range vs. Frequency at Various Loads Rev. 0 | Page 12 of 28 07957-029 -130 -4 07957-028 -140 0.1 -140 ADA4950-1/ADA4950-2 10 0 -10 VOUT, dm = 2V p-p 80 60 40 20 GAIN (dB) 90 45 0 -45 -90 PHASE -135 -180 -225 -270 10G PHASE (Degrees) 07957-036 07957-035 NORMALIZED SPECTRUM (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 29.7 29.8 29.9 30.0 30.1 30.2 FREQUENCY (MHz) 30.3 30.4 30.5 07957-031 GAIN 0 -20 -40 -60 -80 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 31. 30 MHz Intermodulation Distortion -45 -47 -49 -51 CMRR (dB) PSRR (dB) Figure 34. Open-Loop Gain and Phase vs. Frequency 0 RL, dm = 200 VIN = 2V p-p RL, dm = 200 VIN, dm = 100mV p-p -20 -40 PSRR+ -60 PSRR- -80 -53 -55 -57 -59 -61 -63 -65 1 10 100 FREQUENCY (MHz) 07957-032 -100 -120 1000 1 10 100 FREQUENCY (MHz) 1000 Figure 32. CMRR vs. Frequency 0 VOUT, dm = 2V p-p -10 OUTPUT BALANCE (dB) -20 Figure 35. PSRR vs. Frequency 0 -20 -40 CROSSTALK (dB) RL, dm = 200 VIN, dm = 2V p-p -30 -40 -50 -60 -70 1M 10M 100M FREQUENCY (Hz) 1G -60 AMPLIFIER 2 TO AMPLIFIER 1 -80 -100 -120 -140 AMPLIFIER 1 TO AMPLIFIER 2 07957-033 1 10 100 FREQUENCY (MHz) 1000 Figure 33. Output Balance vs. Frequency Figure 36. Crosstalk vs. Frequency, ADA4950-2 Rev. 0 | Page 13 of 28 07957-240 -120 29.6 ADA4950-1/ADA4950-2 0 INPUT SINGLE-ENDED, 50 LOAD TERMINATION OUTPUT DIFFERENTIAL, 100 SOURCE TERMINATION S11: SINGLE-ENDED-TO-SINGLE-ENDED S22: DIFFERENTIAL-TO-DIFFERENTIAL CLOSED-LOOP OUTPUT IMPEDANCE MAGNITUDE () 1k -10 S-PARAMETERS (dB) -20 RL, dm = 200 VIN, dm = 100mV p-p 100 -30 S11 -40 S22 07957-037 10 +OUT -OUT VOUT, dm 1 07957-040 -50 -60 1 10 100 FREQUENCY (MHz) 1000 0.1 0.1 1 10 FREQUENCY (MHz) 100 1k Figure 37. Return Loss (S11, S22) vs. Frequency 1000 OUTPUT VOLTAGE NOISE DENSITY (nV/Hz) Figure 40. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1 15 10 100 G=3 VOLTAGE (V) G=2 5 0 VOUT, dm G=1 10 -5 -10 07957-038 1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) -15 10M 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 TIME (s) Figure 38. Voltage Noise Spectral Density for Various Gains, Referred to Output 0.06 G=1 NORMALIZED OUTPUT VOLTAGE (V) 0.04 NORMALIZED OUTPUT VOLTAGE (V) G=2 G=3 1.0 G=1 G=2 1.5 Figure 41. Overdrive Recovery, G = 2 0.02 0.5 G=3 0 0 -0.02 -0.5 -0.04 07957-039 -1.0 07957-042 -0.06 0 5 10 15 TIME (ns) 20 25 30 -1.5 0 5 10 15 TIME (ns) 20 25 30 Figure 39. Small-Signal Pulse Response for Various Gains Figure 42. Large-Signal Pulse Response for Various Gains Rev. 0 | Page 14 of 28 07957-041 2 x VIN ADA4950-1/ADA4950-2 0.10 2.0 1.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.05 1.0 0.5 0 -0.5 -1.0 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF 07957-046 0 -0.05 CL = 0pF CL = 0.9pF CL = 1.8pF CL = 2.7pF 07957-043 -1.5 -2.0 -0.10 0 5 10 15 TIME (ns) 20 25 30 0 5 10 15 TIME (ns) 20 25 30 Figure 43. Small-Signal Pulse Response for Various Capacitive Loads 0.06 Figure 46. Large-Signal Pulse Response for Various Capacitive Loads 1.5 OUTPUT COMMON-MODE VOLTAGE (V) OUTPUT COMMON-MODE VOLTAGE (V) 0.04 1.0 0.02 0.5 0 0 -0.02 -0.5 -0.04 07957-044 -1.0 07957-047 -0.06 0 5 10 15 TIME (ns) 20 25 30 -1.5 0 5 10 15 TIME (ns) 20 25 30 Figure 44. VOCM Small-Signal Pulse Response 1.5 0.5 0.4 1.0 0.3 PD PIN VOLTAGE (V) Figure 47. VOCM Large-Signal Pulse Response 6 VOCM = +1V DC 5 4 3 2 1 0 07957-045 1.2 1.0 0.8 0.6 0.4 PD PIN INPUT (SHOWN INVERTED FOR CLARITY) 0.2 0 -0.2 NONINVERTING OUTPUT VOLTAGE (V) 07957-048 0.5 VOLTAGE (V) 0.2 ERROR (%) ERROR 0.1 0 -0.1 0 INPUT -0.5 OUTPUT -0.2 -0.3 -0.4 -1.0 -1.5 -5 0 5 10 15 20 TIME (ns) 25 30 35 40 -0.5 -1 0 1 2 3 4 TIME (ms) 5 6 7 8 Figure 45. Settling Time Figure 48. PD Response Time Rev. 0 | Page 15 of 28 ADA4950-1/ADA4950-2 TEST CIRCUITS +5V 250 500 DC-COUPLED SOURCE 50 VIN 53.6 NC 500 VOCM 500 ADA4950-x 1k 25.5 0.1F NC 250 500 07957-049 -5V Figure 49. Equivalent Basic Test Circuit, G = 1 DIFFERENTIAL NETWORK ANALYZER SOURCE 49.9 NC 56.2 250 +5V 500 49.9 DIFFERENTIAL NETWORK ANALYZER RECEIVER 500 50 VOCM 500 56.2 49.9 NC 250 ADA4950-x 50 500 49.9 07957-051 -5V Figure 50. Test Circuit for Output Balance, CMRR +5V 250 500 200 442 CT 2:1 50 DUAL FILTER DC-COUPLED SOURCE 50 VIN LOW-PASS FILTER NC 500 53.6 0.1F VOCM 500 ADA4950-x 261 0.1F 442 25.5 0.1F NC 250 500 07957-252 -5V Figure 51. Test Circuit for Distortion Measurements Rev. 0 | Page 16 of 28 ADA4950-1/ADA4950-2 TERMINOLOGY +INB RGB 250 RGA 500 RGA 500 RGB 250 -IN RF 500 +IN RF 500 -OUT +INA VOCM -INA -INB ADA4950-x +OUT RL, dm VOUT, dm 07957-152 Common-Mode Voltage Common-mode voltage refers to the average of two node voltages with respect to the local ground reference. The output common-mode voltage is defined as VOUT, cm = (V+OUT + V-OUT)/2 Output Balance Output balance is a measure of how close the output differential signals are to being equal in amplitude and opposite in phase. Any imbalances in amplitude or phase produce an undesired common-mode signal at the amplifier output. Output balance error is defined as the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. Figure 52. Signal and Circuit Definitions Differential Voltage Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently, output differential node voltage) is defined as VOUT, dm = (V+OUT - V-OUT) where V+OUT and V-OUT refer to the voltages at the +OUT and -OUT output terminals with respect to a common ground reference. The input differential voltage is defined in different ways, depending upon the selected gain. For G = 1 VIN, dm = (+INA - (-INA)) where +INA and -INA refer to the voltages at the +INA and -INA input terminals with respect to a common ground reference (input terminals +INB and -INB are floating). For G = 2 VIN, dm = (+INB - (-INB)) where +INB and -INB refer to the voltages at the +INB and -INB input terminals with respect to a common ground reference (input terminals +INA and -INA are floating). For G = 3, input terminals +INA and +INB are connected together, and input terminals -INA and -INB are connected together. VIN, dm = (+INAB - (-INAB)) where +INAB and -INAB refer to the voltages at the connection of input terminals +INA and +INB and at the connection of input terminals -INA and -INB with respect to a common ground reference. Output Balance Error = VOUT , cm VOUT , dm Rev. 0 | Page 17 of 28 ADA4950-1/ADA4950-2 THEORY OF OPERATION The ADA4950-x differs from conventional op amps in that it has two outputs whose voltages move in opposite directions and an additional input, VOCM. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The ADA4950-x behaves much like a standard voltage feedback op amp and facilitates single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. Like an op amp, the ADA4950-x has high input impedance at its internal input terminals (to the right of the internal gain resistors) and low output impedance. Because it uses voltage feedback, the ADA4950-x manifests a nominally constant gain bandwidth product. Two feedback loops are used to control the differential and common-mode output voltages. The differential feedback loop, set with on-chip feedback and gain resistors, controls only the differential output voltage. The common-mode feedback loop is internal to the actual amplifier and controls only the commonmode output voltage. This architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. The output common-mode voltage is forced, by the internal common-mode feedback loop, to be equal to the voltage applied to the VOCM input. The internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. This results in differential outputs that are very close to the ideal of being identical in amplitude and that are exactly 180 apart in phase. Rev. 0 | Page 18 of 28 ADA4950-1/ADA4950-2 APPLICATIONS INFORMATION ANALYZING AN APPLICATION CIRCUIT The ADA4950-x uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +INx and -INx (see Figure 52). For most purposes, this voltage can be assumed to be 0. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be 0. Starting from these principles, any application circuit can be analyzed. For G = 3, the +INA and +INB inputs are connected together, and the -INA and -INB inputs are connected together. The differential gain in this case is calculated as follows: G= 500 RF = =3 RG 500 || 250 ESTIMATING THE OUTPUT NOISE VOLTAGE The differential output noise of the ADA4950-x can be estimated using the noise model in Figure 53. The values of RG depend on the selected gain. The input-referred noise voltage density, vnIN, is modeled as a differential input, and the noise currents, inIN- and inIN+, appear between each input and ground. The output voltage due to vnIN is obtained by multiplying vnIN by the noise gain, GN (defined in the GN equation that follows Table 13). The noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. The noise voltage density at the VOCM pin is vnCM. When the feedback networks have the same feedback factor, as is true in most cases, the output noise due to vnCM is common mode. Each of the four resistors contributes (4kTRxx)1/2. The noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by RF/RG. Table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. vnRG1 RG1 RF1 SELECTING THE CLOSED-LOOP GAIN Using the approach described in the Analyzing an Application Circuit section, the differential gain of the circuit in Figure 52 can be determined by VOUT , dm V IN , dm = RF RG where the input resistors (RG) and the feedback resistors (RF) on each side are equal. For G = 1, the +INA and -INA inputs are used, and the +INB and -INB inputs are left floating. The differential gain in this case is calculated as follows: G= R F 500 = =1 RG 500 vnRF1 For G = 2, the +INB and -INB inputs are used, and the +INA and -INA inputs are left floating. The differential gain in this case is calculated as follows: G= R F 500 = =2 RG 250 vnRG2 inIN+ + inIN- vnIN ADA4950-x VOCM vnOD RG2 RF2 vnRF2 Figure 53. Noise Model Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor, RG1 Gain Resistor, RG2 Feedback Resistor, RF1 Feedback Resistor, RF2 Input Noise Term vnIN inIN- inIN+ vnCM vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN- x (RF2) inIN+ x (RF1) vnCM (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Output Multiplication Factor GN 1 1 0 RF1/RG1 RF2/RG2 1 1 Differential Output Noise Voltage Density Term vnO1 = GN(vnIN) vnO2 = (inIN-)(RF2) vnO3 = (inIN+)(RF1) vnO4 = 0 V vnO5 = (RF1/RG1)(4kTRG1)1/2 vnO6 = (RF2/RG2)(4kTRG2)1/2 vnO7 = (4kTRF1)1/2 vnO8 = (4kTRF2)1/2 Rev. 0 | Page 19 of 28 07957-053 vnCM ADA4950-1/ADA4950-2 Table 12. Differential Input, DC-Coupled Nominal Linear Gain 1 2 3 RF () 500 500 500 RG () 500 250 250||500 RIN, dm () 1000 500 333 Differential Output Noise Density (nV/Hz) 9.25 12.9 16.6 Table 13. Single-Ended, Ground-Referenced Input, DC-Coupled, RS = 50 Nominal Linear Gain 1 2 3 1 RF () 500 500 500 RG1 () 500 250 250||500 RT () (Std 1%) 53.6 57.6 61.9 RIN, se () 667 375 267 RG2 ()1 526 277 194 Differential Output Noise Density (nV/Hz) 9.07 12.2 15.0 RG2 = RG1 + (RS||RT). RF +VS RG +IN VOCM Similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the inputreferred terms at +INx and -INx by the appropriate output factor, where: VIN, dm ADA4950-x VOUT, dm 1 = RG1 RG2 and 2 = are the feedback factors. RF1 + RG1 RF2 + RG2 -VS RF Figure 54. ADA4950-x Configured for Balanced (Differential) Inputs When the feedback factors are matched, RF1/RG1 = RF2/RG2, 1 = 2 = , and the noise gain becomes For an unbalanced, single-ended input signal (see Figure 55), the input impedance is RG = RF 1- 2 x (RG + R F ) RF RIN, se RG VOCM RG +VS GN = 1 R =1+ F RG Note that the output noise from VOCM goes to 0 in this case. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. v nOD = 2 v nOi 8 R IN , se i =1 Table 12 and Table 13 list the three available gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations. ADA4950-x RL VOUT, dm RF The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, as shown in Figure 54, the input impedance (RIN, dm) is RIN, dm = (RG + RG) = 2 x RG The value of RG depends on the selected gain. Figure 55. ADA4950-x with Unbalanced (Single-Ended) Input The input impedance of the circuit is effectively higher than it is for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor, RG. The common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider that is formed by RF and RG in the lower loop. This voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across RG in the upper loop and partially bootstrapping RG. Rev. 0 | Page 20 of 28 07957-055 CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT -VS 07957-054 2 GN = is the circuit noise gain. ( 1 + 2 ) RG -IN ADA4950-1/ADA4950-2 Terminating a Single-Ended Input This section describes how to properly terminate a single-ended input to the ADA4950-x with a gain of 1, RF = 500 , and RG = 500 . An example using an input source with a terminated output voltage of 1 V p-p and source resistance of 50 illustrates the steps that must be followed. Note that because the terminated output voltage of the source is 1 V p-p, the open-circuit output voltage of the source is 2 V p-p. The source shown in Figure 56 indicates this open-circuit voltage. 1. The input impedance is calculated using the following formula: RG 500 = = 667 RIN , se = 500 RF 1 - 2 x ( R + R ) 1 - 2 x ( 500 + 500) G F RF RIN, se 667 RS VS 2V p-p 50 RG 500 VOCM RG 500 -VS 07957-156 3. Figure 57 shows that the effective RG in the upper feedback loop is now greater than the RG in the lower loop due to the addition of the termination resistors. To compensate for the imbalance of the gain resistors, add a correction resistor (RTS) in series with RG in the lower loop. RTS is the Thevenin equivalent of the source resistance, RS, and the termination resistance, RT, and is equal to RS||RT. RTS = RTH = RS||RT = 25.9 RS VS 2V p-p 50 RT 53.6 VTH 1.03V p-p RTH 25.9 07957-052 Figure 58. Calculating the Thevenin Equivalent 500 +VS Note that VTH is greater than 1 V p-p, which was obtained with RT = 50 . The modified circuit with the Thevenin equivalent (closest 1% value used for RTH) of the terminated source and RTS in the lower feedback loop is shown in Figure 59. RF 500 +VS ADA4950-x RL VOUT, dm VTH 1.03V p-p RTH 25.5 RG 500 VOCM RG ADA4950-x RL VOUT, dm RF 500 RTS 25.5 500 -VS RF 500 2. To match the 50 source resistance, calculate the termination resistor, RT, using RT||667 = 50 . The closest standard 1% value for RT is 53.6 . RF RIN, se 50 RS RG RT 53.6 500 VOCM RG 500 -VS 500 07957-157 Figure 59. Thevenin Equivalent and Matched Gain Resistors Figure 59 presents a tractable circuit with matched feedback loops that can be easily evaluated. It is useful to point out two effects that occur with a terminated input. The first is that the value of RG is increased in both loops, lowering the overall closed-loop gain. The second is that VTH is a little larger than 1 V p-p, as it would be if RT = 50 . These two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 k), the effects essentially cancel each other out. For small RF and RG, or high gains, however, the diminished closed-loop gain is not canceled completely by the increased VTH. This can be seen by evaluating Figure 59. The desired differential output in this example is 1 V p-p because the terminated input signal is 1 V p-p and the closedloop gain = 1. The actual differential output voltage, however, is equal to (1.03 V p-p)(500/525.5) = 0.98 V p-p. 500 +VS VS 2V p-p 50 ADA4950-x RL VOUT, dm RF Figure 57. Adding Termination Resistor, RT Rev. 0 | Page 21 of 28 07957-059 Figure 56. Calculating Single-Ended Input Impedance, RIN ADA4950-1/ADA4950-2 INPUT COMMON-MODE VOLTAGE RANGE The ADA4950-x input common-mode voltage range is shifted down by approximately one VBE, in contrast to other ADC drivers with centered input ranges such as the ADA4939-x. The downward-shifted input common-mode range is especially suited to dc-coupled, single-ended-to-differential, and singlesupply applications. For 5 V operation, the input common-mode voltage range at the summing nodes of the amplifier is specified as -4.8 V to +3.2 V. With a 5 V supply, the input common-mode voltage range at the summing nodes of the amplifier is specified as +0.2 V to +3.2 V. To avoid nonlinearities, the voltage swing at the +INx and -INx terminals must be confined to these ranges. x1 x1 x1 x4 x1 x4 250 500 +VS x1 x4 x1 x4 250 500 500 VOCM 500 ADA4950-x INPUT AND OUTPUT CAPACITIVE AC COUPLING Although the ADA4950-x is well suited to dc-coupled applications, it is nonetheless possible to use it in ac-coupled circuits. Input ac coupling capacitors can be inserted between the source and RG. This ac coupling blocks the flow of the dc commonmode feedback current and causes the ADA4950-x dc input common-mode voltage to equal the dc output common-mode voltage. The ac coupling capacitors must be placed in both loops to keep the feedback factors matched. Output ac coupling capacitors can be placed in series between each output and its respective load. -VS 07957-253 Figure 60. Input ESD Protection Circuitry SETTING THE OUTPUT COMMON-MODE VOLTAGE The VOCM pin of the ADA4950-x is internally biased with a voltage divider comprising two 50 k resistors across the supplies, with a tap at a voltage approximately equal to the midsupply point, [(+VS) + (-VS)]/2. Because of this internal divider, the VOCM pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. Relying on the internal bias results in an output common-mode voltage that is within approximately 100 mV of the expected value. In cases where more accurate control of the output commonmode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 . If an external voltage divider consisting of equal resistor values is used to set VOCM to midsupply with greater accuracy than produced internally, higher values can be used because the external resistors are placed in parallel with the internal resistors. The input VOCM offset listed in the Specifications section assumes that the VOCM input is driven by a low impedance voltage source. It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC; however, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 10 k to a voltage of nominally midsupply. If multiple ADA4950-x devices share one ADC reference output, a buffer may be necessary to drive the parallel inputs. INPUT SIGNAL SWING CONSIDERATIONS The input terminals of fully differential amplifiers with external gain and feedback resistors connect directly to the amplifier summing nodes; the common-mode voltage swing at these terminals is generally smaller than the input and output swings. In most linear applications, the summing node voltages do not approach levels that result in the forward-biasing of the internal ESD protection diodes on the amplifier inputs. Signals at the inputs of the ADA4950-x are applied to the input side of the gain resistors, and, if caution is not exercised, these signals can be large enough to forward-bias the ESD protection diodes. The four inputs that make up the differential signal paths each have four ESD diodes in series to the negative supply and one diode to the positive supply; the VOCM input has one ESD diode to each supply. Figure 60 illustrates the ESD protection circuitry. Rev. 0 | Page 22 of 28 ADA4950-1/ADA4950-2 LAYOUT, GROUNDING, AND BYPASSING As a high speed device, the ADA4950-x is sensitive to the PCB environment in which it operates. Realizing its superior performance requires attention to the details of high speed PCB design. The first requirement is a solid ground plane that covers as much of the board area around the ADA4950-x as possible. The thermal resistance, JA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD51-7. Bypass the power supply pins as close to the device as possible and directly to a nearby ground plane. Use high frequency ceramic chip capacitors. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 F) be used for each supply. Place the 1000 pF capacitor closer to the device. Farther away, provide low frequency bulk bypassing using 10 F tantalum capacitors from each supply to ground. Signal routing should be short and direct to avoid parasitic effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When routing differential signals over a long distance, keep PCB traces close together, and twist any differential wiring to minimize loop area. Doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 0.80 1.30 0.80 Figure 61. Recommended PCB Thermal Attach Pad (Dimensions in Millimeters) 1.30 TOP METAL GROUND PLANE 0.30 PLATED VIA HOLE POWER PLANE 07957-057 BOTTOM METAL Figure 62. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters) Rev. 0 | Page 23 of 28 07957-056 ADA4950-1/ADA4950-2 HIGH PERFORMANCE ADC DRIVING The ADA4950-x is ideally suited for broadband dc-coupled applications. The circuit in Figure 63 shows a front-end connection for an ADA4950-1 driving an AD9245 ADC, with dc coupling on the ADA4950-1 input and output. (The AD9245 achieves its optimum performance when driven differentially.) The ADA4950-1 eliminates the need for a transformer to drive the ADC and performs a single-ended-todifferential conversion and buffering of the driving signal. The ADA4950-1 is configured with a single 3.3 V supply and a gain of 2 for a single-ended input to differential output. The 57.6 termination resistor, in parallel with the single-ended input impedance of 375 , provides a 50 termination for the source. The additional 26.7 Thevenin resistance added to the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. The required Thevenin bias voltage of 0.27 VDC applied to the lower loop is obtained by scaling the VREF output of the AD9245 and buffering it with the AD8031. In this example, the 50 signal generator has a 1 V p-p unipolar open-circuit output voltage, and 0.5 V p-p output voltage when terminated in 50 . The VOCM input is bypassed for noise reduction and set externally with 1% resistors to maximize output dynamic range on the tight 3.3 V supply. +3.3V VOUT, dm = 1V p-p VOUT, cm = +1.65V 1.0V 0.5V 0V 50 1.0V p-p UNIPOLAR SIGNAL SOURCE 57.6 10k NC 500 VOCM NC 500 33 VIN- AVDD 250 500 0.1F 0.1F Because the inputs are dc-coupled, dc common-mode current flows in the feedback loops, and a nominal dc level of 0.76 V is present at the amplifier input terminals. A fraction of the output signal is also present at the input terminals as a common-mode signal; its level is equal to the ac output swing at the noninverting output, divided down by the feedback factor of the lower loop. In this example, this ripple is 0.5 V p-p x [276.7/(276.7 + 500)] = 0.18 V p-p. This ac signal is riding on the 0.76 V dc level, producing a voltage swing between 0.67 V and 0.85 V at the input terminals. This is well within the specified limits of 0.2 V to 1.5 V. With an output common-mode voltage of 1.65 V, each ADA4950-1 output swings between 1.4 V and 1.9 V, opposite in phase, providing a gain of 2 and a 1 V p-p differential signal to the ADC input. The differential RC section between the ADA4950-1 output and the ADC provides single-pole low-pass filtering and extra buffering for the current spikes that are output from the ADC input when its SHA capacitors are discharged. The AD9245 is configured for a 1 V p-p full-scale input by connecting its SENSE pin to VREF, as shown in Figure 63. ADA4950-1 20pF 33 VIN+ AD9245 VREF SENSE AGND 0.1F 10k 250 26.7 500 0.1F 10F + 866 0.1F AD8031 07957-254 0.1F 1.0k 0.1F 10F + Figure 63. ADA4950-1 Driving an AD9245 ADC with Unipolar DC-Coupled Input and Output, Gain = 2 Rev. 0 | Page 24 of 28 ADA4950-1/ADA4950-2 OUTLINE DIMENSIONS 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 072208-A 0.60 MAX 0.50 0.40 0.30 13 16 12 (BOTTOM VIEW) 1 EXPOSED PAD PIN 1 INDICATOR *1.45 1.30 SQ 1.15 9 8 5 4 0.25 MIN 1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-2) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 19 18 EXPOSED PAD (BOTTOM VIEW) PIN 1 INDICATOR 24 1 PIN 1 INDICATOR TOP VIEW 3.75 BSC SQ 2.25 2.10 SQ 1.95 6 13 12 7 0.25 MIN 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 2.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 072208-A SEATING PLANE 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 Figure 65. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-1) Dimensions shown in millimeters ORDERING GUIDE Model ADA4950-1YCPZ-R2 1 ADA4950-1YCPZ-RL1 ADA4950-1YCPZ-R71 ADA4950-2YCPZ-R21 ADA4950-2YCPZ-RL1 ADA4950-2YCPZ-R71 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Package Option CP-16-2 CP-16-2 CP-16-2 CP-24-1 CP-24-1 CP-24-1 Ordering Quantity 250 5,000 1,500 250 5,000 1,500 Branding H1L H1L H1L Z = RoHS Compliant Part. Rev. 0 | Page 25 of 28 ADA4950-1/ADA4950-2 NOTES Rev. 0 | Page 26 of 28 ADA4950-1/ADA4950-2 NOTES Rev. 0 | Page 27 of 28 ADA4950-1/ADA4950-2 NOTES (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07957-0-5/09(0) Rev. 0 | Page 28 of 28 |
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